The Design of Optimized RISC Processor for Edge Artificial Intelligence Based on Custom Instruction Set Extension

Edge computing is becoming increasingly popular in artificial intelligence (AI) application development due to the benefits of local execution. One widely used approach overcome hardware limitations edge heterogeneous computing, which combines a general-purpose processor with domain-specific AI processor. However, this can be inefficient communication overhead resulting from complex protocol. To avoid overhead, concept an application-specific instruction set based on customizable architecture (ISA) has emerged. By integrating into core, on-chip replaces Further, custom extension (ISE) reduces number instructions needed execute applications. In paper, we propose uniprocessor system for lightweight systems. First, define ISE integrate and GPP single processor, minimizing overhead. Next, designed integrated core architecture, including base implemented FPGA. Finally, evaluated proposed through simulation implementation The results show that consumed 6.62% more lookup tables 74% fewer flip-flops while achieving up 193.88 times enhanced throughput performance 52.75 energy efficiency compared previous system.